Exemplary embodiments of this invention relate to a standard cell library that includes a plurality of types of standard cells, a method of designing semiconductor integrated circuits utilizing standard cells, a semiconductor integrated circuit pattern including a circuit block in which a plurality of types of standard cells is arranged, and a semiconductor integrated circuit in which the semiconductor integrated circuit pattern is formed on a semiconductor substrate.
In the design of semiconductor integrated circuits using standard cell technology, a plurality of types of standard cells having various functions is prepared in a library. In these standard cells, patterns in a plurality of layers necessary to realize respective functions are arranged in respective cell frames. Each of the cell frames has the same height and a width of a unit width multiplied by an integer. Some of the plurality of types of standard cells that are required to meat the specification are selected and are arranged in vertical and horizontal directions with their frame boundaries contacting each other. The structure and the arrangement method of the standard cell are explained in, for example, Japanese Laid-open Patent 2005-72133 (Patent Document 1).
In order to suppress excessive leakage current and to realize necessary operation speed, on the other hand, it becomes common to construct semiconductor integrated circuits with transistors having different threshold voltages. That is, high threshold voltage transistors, which have low operation speed and low leakage current, are used in circuits and signal transmission paths that do not need high operation speed, while low threshold voltage transistors, which have high leakage current and high operation speed, are used in circuits and signal transmission paths that need high operation speed.
For example, Japanese Laid-open Patent 2004-172627 (Patent Document 2) proposes, in FIG. 15, to add a process step to additionally distribute impurities under the gate electrodes of high threshold voltage transistors. Thus, according to this reference, threshold voltages of MOSFETs that constitute logic gates in arbitrary positions in a semiconductor integrated circuit can be modified freely.
However, the study by the inventors of this application has indicated that a restriction may be applied to the arrangement of the standard cells if the technology that the transistors with different threshold voltages are formed by addition of impurity, as proposed in the Patent Document 2, is applied to the standard cell technology.
FIG. 12 is a layout diagram showing an example of a conventional standard cell. In FIG. 12, within a cell frame 112 shown with a solid line, patterns in a plurality of layers required for realizing the function of the standard cell 110 is arranged. The standard cell 110 shown in FIG. 12 has a function of an inverter, and the patterns in some of the plurality of layers, i.e., N-well pattern 114, active region patterns 116 and 118, gate pattern 120, and P-channel threshold voltage adjusting pattern 122 and N-channel threshold voltage adjusting pattern 124 are shown. The patterns in other layers are omitted.
An N-well pattern 114 is provided on the upper side of FIG. 12. The N-well pattern 114 extends from inside of the cell frame 112 to the outside of the upper boundary 112a and the left and right boundaries 112c, 112d of the cell frame. The portion extending to the outside of the cell frame 112 will be merged when a plurality of standard cells is placed to form a circuit block such that the boundaries of their cell frames are in contact with each other.
A first active region pattern 116 is provided within the N-well pattern 114, and a gate electrode pattern 120 that goes through over the first active region pattern 116 in the vertical direction is also provided. These are patterns for forming a P-channel MOS transistor (a PMOS transistor) 140 on a semiconductor substrate. That is, a channel region 142 of the PMOS transistor 140 is formed at the portion where the gate electrode pattern 120 overlaps the first active region pattern 116. Further, a source region 144 and a drain region 146 of the PMOS transistor 140 are formed on both sides of the gate electrode pattern 120 within the first active region pattern 116.
A P-well is formed outside of the N-well pattern 114, or on the lower side of FIG. 12. That is, an impurity for forming the P-well is doped by using a mask that is formed by a reversed data of the N-well pattern 114. And an N-channel MOS transistor (an NMOS transistor) 150 is formed by a second active region pattern 118 arrange on the lower side of FIG. 12 and the gate electrode pattern 120 that goes through over the second active region pattern 118 in the vertical direction. A channel region 152 of the NMOS transistor 150 is formed at the portion where the gate electrode pattern 120 overlaps the second active region pattern 118. A source region 154 and a drain region 156 of the NMOS transistor 150 are formed on both sides of the gate electrode pattern 120 within the second active region pattern 118.
Here, the threshold voltages of the PMOS transistor 140 and the NMOS transistor are determined by impurity concentrations of the respective channel region. For example, the higher the respective impurity concentrations, the higher the threshold voltages.
The standard cell 110 shown in FIG. 12 included a first threshold voltage adjusting pattern 122 and a second threshold voltage adjusting pattern 124 for adjusting the threshold voltages of the PMOS transistor 140 and the NMOS transistors 150. The first threshold voltage adjusting pattern 122 is a pattern for forming a mask that is used for adjusting the threshold voltage of the PMOS transistor 140 by additionally doping impurities in the channel region 142 of the PMOS transistor 140. The second threshold voltage adjusting pattern 142 is a pattern for forming a mask that is used for adjusting the threshold voltage of the NMOS transistor 150 by additionally doping impurities in the channel region 152 of the NMOS transistor 150.
In practice, two standard cells that are the same except for having or not having the first and the second threshold voltage adjusting patterns 122 and 124 are prepared. These cells have the common function, but the threshold voltages of the PMOS transistor 140 and the NMOS transistor 150 are different with each other.